Semiconductor memories in general, and SRAMs in particular, present the constant challenge of increasing density while maintaining manufacturability and increasing access speed. Many architectural, circuit and process innovations have been introduced to satisfy one or more of these goals.
In divided word line architectures, the memory array is subdivided into blocks. Each block contains all of the rows of the array, but only some of the columns thereof. Low resistivity global word lines, typically metal, span the entire array in the row direction. A row decoder selects a particular one of the global word lines in response to an address. In addition, a block decoder provides block select signals in response to the address, indicating which one or more of the blocks is to be accessed. The selected global word line interacts with the block select signals to select one or more local word lines. The local word lines are typically comprised of a higher resistivity material such as polysilicon. The divided word line technique generally allows the length of the local word lines to be minimized, thus minimizing the word line RC product and providing faster access times.
However, as the density of memories utilizing a divided word line architecture increases, some aspects of their design become troublesome. For instance, one example of a 256K SRAM organized as a 32K-by-8 array (referred to as byte-wide), divides the array into 16 blocks. Each block comprises 512 rows and 32 columns. Each block is provided with eight first stage, or local, sense amplifiers. Because of the large number of sense amplifiers, their size is necessarily small, thus preventing the designer from optimizing the sense amplifier design.
Other problems which become apparent primarily in byte-wide, divided word line memories include increased data line length, both in the local data lines (prior to the first stage sense amplifiers) and the global data lines (between the first and second stage sense amplifiers).